Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. PLDs typically include an array of configurable logic elements that are programmably interconnected to each other and to programmable input/output blocks via some form of programmable interconnect. This collection of configurable logic may be customized by loading configuration data into internal configuration memory cells that define how the logic elements, interconnect, and input/output blocks are configured. The configuration memory is typically implemented using static random access memory (SRAM). Presently, the address voltage for SRAM memory cells in a PLD is held constant across process, voltage and temperature (PVT). However, in some cases, a flat address supply voltage during read has significantly reduced the voltage difference between read and read margin across PVT. There exists a need for a new read scheme for SRAM memory cells in a programmable device, such as a PLD.